module pc_reg(
           input wire clk,
           input wire rst,
           output reg [31: 0] pc_o,

           //from ctrl
           input wire [31: 0] jump_addr_i,
           input wire jump_en
       );
//pc生成模块
//cpu 32位，rom每位存8bit

reg rst_r, rst_rr;
always@(posedge clk or negedge rst_rr)
	begin
		if (!rst_rr)
			pc_o <= 32'b0;
		else if (jump_en)
			pc_o <= jump_addr_i;
		else
			pc_o <= pc_o + 3'd4;
	end


always@(posedge clk or negedge rst)
	begin
		if (!rst)
			{rst_rr, rst_r} <= 2'd0;
		else
			{rst_rr, rst_r} <= {rst_r, rst};
	end

endmodule
